An embodiment relates generally to a method of manufacturing a flash memory device and, more particularly, to a method of manufacturing a flash memory device that is capable of improving the charge distribution of a floating gate by forming a polysilicon layer for a floating gate with a uniform distribution of grains, each having a small grain size.
To increase the storage capacity of a flash memory device, research has been carried out on the development of a multi-level cell (MLC) whose charge storage capacity per cell is increased from 1 bit to 2 to 4 bits. To manufacture a device having the charge storage capacity of 2 to 4 bits, very strict charge distribution criteria must be satisfied. To satisfy the charge distribution criteria, a polysilicon layer for a floating gate having a uniform distribution of grains, each having a small grain size must be formed.
To implement the polysilicon layer for a floating gate, an undoped polysilicon layer is formed and a doped polysilicon layer is formed over the undoped polysilicon layer. Importantly, the undoped polysilicon layer must be formed as thin as possible in order to reduce the grain size, and must have a thickness of 100 Å or less to greatly improve the charge distribution of the floating gate. Where the undoped polysilicon layer is thinly formed, the undoped polysilicon layer is grown in the form of an island to thereby form a discontinuous thin film, or a continuous thin film is formed with a surface that is very coarse (i.e., not smooth).